1. Field of the Invention
The present invention is generally related to nonvolatile memory device, and more particularly, to a dual reference cell sensing scheme for nonvolatile memory.
2. Description of Related Art
Non-volatile memory devices are memory devices that can store data even when voltage is cut off. These nonvolatile memory devices are particularly useful in portable devices for storing operating system as well as user data. Recently, high attention and heavy research have been given to non-volatile memory because of its adaptability and flexibility. The speed of the memory is of great importance for non-volatile memory.
Erasable programmable read only memories (EPROMs) are a fast growing class of non-volatile storage integrated circuits because they have the ability of electrically programming and reading a memory cell in the chip. EPROMs frequently use memory cells that have electrically isolated gates commonly referred to as floating gates. These floating gates are most often completely surrounded by oxide and formed from a polycrystalline silicon (i.e., polysilicon) layer. Information is stored in the memory cells or devices in the form of a charge on the floating gate. Charges are transported to the floating gates by a variety of mechanisms such as avalanche injection, channel injection, tunneling, etc., depending on the construction of the cells. These cells are generally erased by exposing the array to ultraviolet (UV) radiation.
Electrically erasable and programmable read only memories (EERPOMs) are both electrically erasable and electrically programmable. Charges are placed onto and removed from a floating gate via tunneling of electrons through a thin gate oxide region formed over the substrate. In other instances, charges are removed through an upper control electrode.
More recently, a new category of electrically erasable devices has emerged, and the devices are frequently referred to as “flash” EPROMs or “flash” EEPROMs. In these memories, memory cells are erased electrically, whereas the cells themselves include only a single device per cell. Also, erasing of the entire array or a block of individual memory cells may be accomplished.
In accomplishing erase and program verification, a variety of sense amplifiers are used in the prior art to sense the state of the memory cells. To accomplish verification by sensing, a current is generated by the memory cell being verified by application of a gate potential to its word line. The current is compared to a current from a reference cell by the sense amplifier. Typically, EPROMs employ a column of UV-erased cells, identical in structure to the memory cells, which act as these reference cells. The sense amplifier determines whether the memory cell being verified is drawing more or less current than the reference cell which is weighted in some relationship to the memory cell. In doing so, the sense amplifier verifies the programmed state of the memory cell. The following equation defines the change in potential for a single cell reference scheme:ΔVsingle=Vref(H)−Vcell or ΔVsingle=Vcell−Vref(L)  (1) 
The reading speed of the non-volatile memory depends on the sensing scheme of the sense amplifiers. Prior art uses a single cell reference scheme for the sense amplifiers and therefore it is not suitable for low voltage application due to the unstable reference voltage and a narrow sensing window of the single cell reference scheme. Furthermore the dummy cell method and trimming method used in the prior art for setting the reference cell are expensive and inaccurate. Therefore, there is a need for a non-volatile memory with high speed read sped.